Example 6: Project Options
5-8 Getting Started with ADSP-BF548 EZ-KIT Lite
The other generated C file (
Example_6_cplbtab.c) does require modifica-
tion—this has already been done in the Example_6.dpj project file
distributed with VisualDSP++ 5.0: the properties of the data cache CPLB
entries covering the FSS heap and frame buffers for the LCD have been
changed to disable caching (Listing 5-2). The startup code that runs
before main() transfers the contents of the CPLB tables into the appropri-
ate internal registers of the ADSP-BF548 processor before enabling the
caches.
Listing 5-2. Example_6_cplbtab.c File
...
// CPLBs covering 48MB
{0x01000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
{0x01400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
{0x01800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
// LCD frame (DMA use)
{0x01c00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE)},
{0x02000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
{0x02400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
{0x02800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
// LCD frame (DMA use)
{0x02c00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE)},
// FSS Heap (DMA use)
{0x03000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE)},
{0x03400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
{0x03800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
{0x03c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
...
...
