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8 ELECTRICAL CHARACTERISTICS
S1C33210 PRODUCT PART EPSON A-81
DRAM random access cycle (basic cycle)
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1
Next data transfer
CAS1 PRE1(precharge) RAS1' CAS1'
tAD tAD tAD
tCASD2tCASD1
tRDS
tACCF
tRACF
tRDH
tRASD2tRASD1
tRASW
tRDD3tRDD1
tRDW2
tWRD3tWRD1
tWRW2
tWDD1 tWDD2
tCASW
tCACF
1
1 tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals.
DRAM fast-page access cycle
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1 Data transfer #2 Next data transfer
CAS1 CAS2 PRE1(precharge) RAS1'
tAD tAD tAD
tRDS
tACCF
tRACF
tRDH
tRASD2tRASD1
tRDD3tRDD1
tWRD3tWRD1
tWDD1 tWDD2 tWDD2
tCACF tACCF
tRASW
tRDW2
tCASD2tCASD1
tRDS tRDH
tCASW
tWRW2
11
1 tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals.